(1) Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a data read-out circuit which has a wide operation margin and operates with low power consumption.
(2) Description of the Related Art
As a non-volatile semiconductor memory device, there has been known a semiconductor memory device using as a memory cell a MOS field effect transistor (hereinafter referred to as "MOSFET") which has a two-layered gate-structure, for example, a floating gate and a control (regular) gate. FIG. 1 is a cross-sectional view showing such a kind of memory cell, and FIG. 2 is a symbolic diagram of such memory cell. The memory cell shown in FIG. 1 has N-type source/drain diffusion layers 72 and 73 on its P-type semiconductor substrate 71, and also has a floating gate 74 which is electrically insulated from outside by an insulating layer (not shown) provided on the substrate 71, and a control gate 75 for controlling the switching operation of the memory cell.
This memory cell becomes conductive with a low control voltage (e.g. 2 V), as shown with a solid line 91 in FIG. 3, when the floating gate 74 is electrically in a neutral state (hereinafter referred to as "non-written state"), but a threshold voltage of the memory cell seen from the control gate 75 becomes high (hereinafter referred to as "written state") as electrons are injected to the floating gate 74 when a high voltage (e.g. 12.5 V) is applied to the control gate 75 and the drain 73 and electrons are injected to the floating gate 74. Thus, as shown with a solid line 92 in FIG. 3, the memory cell does not become conductive unless a high voltage (e.g. 7 V) is applied to the control gate 75 of the memory cell. Data can be stored with the utilization of this change in the threshold voltage.
FIG. 4 is a circuit diagram showing a data read-out circuit in a conventional non-volatile semiconductor memory device which uses the above mentioned memory cells. The conventional non-volatile semiconductor memory device has a memory cell array MA5 including a plurality of memory cells MC11.about.MCmn in a matrix form therein whose drains are connected to a plurality of column lines D1.about.Dn and whose gates are connected to a plurality of row lines SX1.about.SXm functioning as common gate electrodes. The row lines SX1.about.SXm selectively control the memory cells by the row selection signals from a row decoder XD5.
The column lines D1.about.Dn are connected to an input node SIN5 of a sense circuit SA5 through a column selection circuit YS5 which is formed by N-channel MOSFETs MY1.about.MYn, and these N-channel MOSFETs MY1.about.MYn are selectively on-off controlled by column selection signals SY1.about.SYn from a column decoder YD5.
In the sense circuit SA5, the input node SIN5 is connected to a source of an N-channel MOSFET MN51 and also an input terminal of an inverter circuit INV51, and an output terminal of the inverter circuit INV51 is connected to a gate of this N-channel MOSFET MN51. The source of a P-channel MOSFET MP51 which operates as a load MOSFET is connected to a power supply source Vc, and the gate and drain thereof are commonly connected to the drain of the N-channel MOSFET MN51. An output node V.sub.SA5 of this sense circuit SA5 is defined between the drain of the N-channel MOSFET MN51 and the common gate/drain of the P-channel MOSFET MP51.
A reference voltage generation circuit RA5 which is formed by an N-channel MOSFET MN52, an inverter circuit INV52 and a P-channel MOSFET MP52 has an identical circuit configuration as that of the above described sense circuit SA5. An input node of this reference voltage generation circuit RA5 is connected, through an N-channel MOSFET MYR5 which is equivalent to each of the N-channel MOSFETs MY1.about.MYn constituting the column selection circuit YS5, to a reference memory cell MCR5 which is equivalent to each of the memory cells MC11.about.MCmn. The reference voltage generation circuit RA5 outputs a reference voltage V.sub.RA5.
A comparison amplifier AMP5 is formed by one series circuit of a P-channel MOSFET MP53 and an N-channel MOSFET MN53 and the other series circuit of a P-channel MOSFET MP54 and an N-channel MOSFET MN54, each of the series circuits being connected between the power supply source Vc and the ground potential source Vs. The gate of the N-channel MOSFET MN53 is connected to the gate and the drain of the N-channel MOSFET MN54, thereby constituting a current-mirror circuit. The sense output V.sub.SA5 from the sense circuit SA5 is supplied to the gate of the P-channel MOSFET MP53, and the reference output V.sub.RA5 from the reference voltage generation circuit RA5 is supplied to the gate of the P-channel MOSFET MP54. The junction node between the drain of the P-channel MOSFET MP53 and the drain of the N-channel MOSFET MN53 is connected to an output terminal DAT5.
Next, an operation of the above described data read-out circuit is explained. For instance, when the memory cell MC11 in the memory cell array MA5 is to be selected, the row line SX1 is selected by the row decoder XD5, and the column line D1 is selected through the N-channel MOSFET MY1 by the column decoder YD5. As a result, the memory cell MC11, which is located at the intersection of the selected row line SX1 and the column line D1, is connected to the input node SIN5.
When this selected memory cell MC11 is in its non-written state, the column line D1 and the input node SIN5 of the sense circuit SA5 are discharged through the memory cell MC11, so that the potential at the input node SIN5 becomes low. Consequently, the output of inverter circuit INV51 turns to a high voltage and the N-channel MOSFET MN51 becomes conductive accordingly. As a result, the potential of the output V.sub.SA5 of the sense circuit SA5 turns to a lower level, too.
To the contrary, when the selected memory cell MC11 is in the written state, the column line D1 and the input node SIN5 of the sense circuit SA5 are changed through the P-channel MOSFET MP51 and the N-channel MOSFET MN51, so that the potential at the input node SIN5 of the sense circuit SA5 becomes high. Consequently, the output of the inverter circuit INV51 becomes a low level, thereby causing the N-channel MOSFET MN51 to become a non-conductive state, and accordingly the output V.sub.SA5 of the sense circuit SA5 turns to a high level by the P-channel MOSFET MP51.
The reference voltage generation circuit RA5 outputs an output V.sub.RA5 of low level because the connected reference memory cell MCR5 is in the non-written state and its gate electrode is connected to the power supply source Vc and is in its conductive state.
The sense output V.sub.SA5 from the sense circuit SA5, which changes according to the state of the selected memory cell among the cells MC11.about.MCmn, is compared with the potential of the reference output V.sub.RA5 of the reference voltage generation circuit RA5 by the comparison amplifier AMP5, whereby the output data DAT5 is obtained.
In the actual products of the semiconductor memory devices, the desired characteristics are realized by so designing that the characteristics of each of the memory cells MC11.about.MCmn in the non-written state and the characteristics of the reference memory cell MCR5 are identical, that the characteristics of the elements constituting the sense circuit SA5 and the characteristics of the elements constituting the reference voltage generation circuit RA5 are identical, that the characteristics of the P-channel MOSFETs MP53, MP54 in the comparison amplifier AMP5 are identical, and that the mutual transfer conductance of the N-channel MOSFETs MN53, MN54 constituting the current-mirror circuit are appropriately set.
For example, assuming that the respective mutual transfer conductance of the N-channel MOSFETs MN53, MN54 are gm.sub.(MN53), gm.sub.(MN54), respectively, the gm.sub.(MN54) is designed one half the gm.sub.(MN53).
The characteristics of the comparison amplifier AMP5 having the above conditions are shown in FIG. 5. In FIG. 5, the abscissa is the output voltage V.sub.DAT5 at the output terminal DAT5 of the comparison amplifier AMP5 and the ordinate is the current. Here, the current flowing in the N-channel MOSFET MN53 is shown by I.sub.MN53, the current flowing in the P-channel MOSFET MP53, in the case where the selected memory cell is in the non-written state, is shown by I.sub.MP53A, and the same, in the case where the selected memory cell is in the written state, is shown by I.sub.MP53B (normally 0 A). Thus, by making the mutual transfer conductance gm.sub.(MN54) one half the mutual transfer conductance gm.sub.(MN53), the current I.sub.MN53 takes an intermediate level between the current I.sub.MP53A and I.sub.MP53B, and when the selected memory cell is in the non-written state, the output voltage V.sub.DAT5 at the output terminal DAT5 is V51 which is the intersection of the current I.sub.MN53 and I.sub.MP53A, and when the selected memory cell is in the written state, the output voltage V.sub.DAT5 is the ground potential voltage Vs which is the intersection of the current I.sub.MN53 and I.sub.MP53B.
In the data read-out circuit in the conventional semiconductor memory device having the above explained circuit configuration, the output voltage V.sub.RA5 from the reference voltage generation circuit RA5 is constant, and therefore, the current which flows, according to the output voltage V.sub.RA5, in the N-channel MOSFET MN53 of the comparison amplifier AMP5 takes an intermediate level, as shown by I.sub.MN53 in FIG. 5, between the current I.sub.MP53A which flows in the P-channel MOSFET MP53 when the selected memory cell is in the non-written state and the current I.sub.MP53B which flows in the same P-channel MOSFET MP53 when the selected memory cell is in the written state. As a result, the high level output obtained at the output terminal DAT5 goes up only to the voltage V52 which is lower than the power supply voltage Vc and, in the case where the output V.sub.DAT5 is to be turned to a high level, the capacitance parasitic to the output terminal DAT5 has to be charged by the current of I.sub.MP53A -I.sub.MN53. When the output voltage V.sub.DAT5 is to be turned to a low level, the charge in the capacitance parasitic to the output terminal DAT5 has to be discharged by the current of I.sub.MN53 -I.sub.MP53B, but when the output voltage V.sub.DAT5 is to be turned to a high level, the through-current flows from the power supply source Vc to the ground potential source Vs through the P-channel MOSFET MP53 and the N-channel MOSFET MN53, thereby increasing the consumption of current. Further, in order to make the speed of charging and discharging of the output terminal DAT5 higher, it is necessary to set the currents I.sub.MP53A and I.sub.MN53 larger, which also presents a problem of increasing the current. These are problems to be solved in the conventional data read-out circuit.